1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a method of fabricating a semiconductor device having an etch stop layer between a bit line pattern and a buried contact plug, and a related device.
2. Description of the Related Art
As memory devices, such as Dynamic Random Access Memory (DRAM), becomes more highly integrated and have very high speeds, a reduction in contact resistance is necessarily required. DRAM devices have a landing pad, a bit line, a bit contact plug, a buried contact plug, and a storage node. A metal material such as tungsten is widely used as the bit line. Further, the bit line is connected to a lower conductive pattern such as the landing pad via the bit contact plug. Polysilicon is widely employed as the layer-forming material of the landing pad. Technology regarding the forming of metal silicide between the bit contact plug and the landing pad has been researched in order to reduce the contact resistance.
FIGS. 1 to 3 are cross-sectional views illustrating a method of fabricating a conventional semiconductor device having a bit line and a buried contact plug.
Referring to FIG. 1, an isolation layer 13 is formed within a semiconductor substrate 11 to define an active region 12. A lower interlayer dielectric layer 15 is formed on the surface of the semiconductor substrate 11 having the isolation layer 13. First and second landing pads 16 and 17 are formed through the lower interlayer dielectric layer 15 to contact the active region 12. The landing pads 16 and 17 are formed of a polysilicon layer. Top surfaces of the landing pads 16 and 17 and a top surface of the lower interlayer dielectric layer 15 are formed to be at approximately the same level.
An intermediate interlayer dielectric layer 25 is formed on the surface of the semiconductor substrate 11 having the landing pads 16 and 17. A bit contact hole is formed through the intermediate interlayer dielectric layer 25 to expose the second landing pad 17. A bit plug spacer 21 is formed on the sidewalls of the bit contact hole. A silicidation process is then carried out to form a metal silicide layer 18 in the second landing pad 17 exposed at the bottom of the bit contact hole. In this case, the top surface of the metal silicide layer 18 is disposed on substantially the same level as the top surface of the first landing pad 16 and the top surface of the lower interlayer dielectric layer 15.
Subsequently, a metal layer is formed, which fills the bit contact hole and covers the intermediate interlayer dielectric layer 25. The metal layer is formed of a tungsten layer. A hard mask pattern 31 is formed on the metal layer. The metal layer is patterned to form a bit line 29. As a result, a bit contact plug 23 is formed within the bit contact hole. The bit line 29 is electrically connected to the metal silicide layer 18 and the second landing pad 17 via the bit contact plug 23. A bit line spacer 27 is formed on the sidewalls of the bit line 29 and the hard mask pattern 31. An upper interlayer dielectric layer 35 is formed on the surface of the semiconductor substrate 11 having the bit line 29.
Referring to FIG. 2, the upper interlayer dielectric layer 35 and the intermediate interlayer dielectric layer 25 are patterned to form a buried contact hole 37 exposing the first landing pad 16. An isotropic etching process is then carried out to extend the buried contact hole 37.
While the buried contact hole 37 is extended, the lower interlayer dielectric layer 15 is partially etched to form a recess. In addition, the metal silicide layer 18 is partially exposed. The metal silicide layer 18 generally has a high etch rate with respect to the isotropic etching process. Thus, the metal silicide layer 18 is also partially etched by the isotropic etching process so that an air gap 18H is formed. Consequently, the contact area between the bit contact plug 23 and the metal silicide layer 18 may be significantly reduced due to the air gap 18H.
Referring to FIG. 3, an insulating spacer 39 is formed on the sidewalls of the extended buried contact hole 37. The insulating spacer 39 is formed of an insulating layer such as a silicon nitride layer. While the insulating spacer 39 is formed, the insulating layer also penetrates into the air gap 18H to form a contact barrier layer 18S.
A buried contact plug 41 is then formed, which fills the extended buried contact hole 37. A storage node 43 is formed on the buried contact plug 41.
According to the conventional method of fabricating a semiconductor device as described above, the contact resistance between the bit contact plug 23 and the metal silicide layer 18 may substantially increase due to the reduced contact surface area and the presence of the contact barrier layer 18S. Accordingly, it may be difficult to control the contact resistance between the bit contact plug 23 and the metal silicide layer 18 in a conventional method of forming the contact plug.
Meanwhile, other methods of forming the contact plug are disclosed in U.S. Patent Application Publication No. 2005/0037590 A1 entitled “Semiconductor Device and Method for Manufacturing Same” to Inoue, et al.
According to Inoue, et al., a first interlayer dielectric layer is formed on a semiconductor substrate. A plurality of bit lines are formed on the first interlayer dielectric layer. A second interlayer dielectric layer is disposed between the bit line and the first interlayer dielectric layer. A nitride layer is formed, which covers sidewalls and a top surface of the bit line and covers sidewalls of the second interlayer dielectric layer. A third interlayer dielectric layer is formed on the semiconductor substrate having the nitride layer. A capacitor contact plug is disposed between the bit lines, which sequentially penetrates the third interlayer dielectric layer and the nitride layer. Accordingly, the capacitor contact plug is insulated from the bit lines by the nitride layer.
However, a technique of forming the buried contact plug between the bit lines so as to generate a contact surface as large as possible between the contact plug and the landing pad while preventing the landing pad below the bit line from being damaged is still required.